Design and analysis of partition technique based Dadda multiplier architecture
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Author |
D. Kalaiyarasi, T. Suguna, C. Padma, C. Nalini, M. Sundar Raj and G. Nagarajan
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e-ISSN |
1819-6608 |
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On Pages
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113-120
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Volume No. |
20
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Issue No. |
3
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Issue Date |
March 21, 2025
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DOI |
https://doi.org/10.59018/022523
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Keywords |
column compression, dadda multiplier, mux based full adder, mux based half adder, binary to excess-1 convertor.
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Abstract
This paper combines two design strategies to speed up column compression multiplication using the Dadda algorithm: decomposing partial products into two sections so that they can be compressed individually in parallel columns and added more quickly using a ripple carry adder and a Binary to Excess-1 converter. This paper also proposes multiplexer based full adder and a half adder designs to optimize power dissipation and propagation delay. The proposed Dadda multiplier of size 8,16,32 and 64 is designed by employing proposed adder designs and is simulated and synthesized using Altera Quartus II with EP2S15F484C3 device for 90nm technology of supply voltage of 1.2V and observed the performance parameters such as delay, power, Maximum Usable Frequency (MUF), Power Delay Product (PDP) and area respectively. It is observed that the proposed partitioned Dadda multiplier in this work,on an average, was able to minimize ALUTs utilization by 73.16%, delay by 51.57%, power by 47.38%, PDP by 73.89% and MUF in an average is increased by 51.57% when compared to existing works. It is concluded that the suggested multiplier can be employed in applications where power and propagation delay are of major concerns since the proposed multiplier design has substantially optimized for all the performance parameters than the conventional Dadda multiplier.
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