Design and analysis of 3-NM strained and conventional FinFETs
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Author |
Kim Ho Yeap, Pei Xin Tan, Han Kee Lee, Siu Hong Loh, Nuraidayani Effendy, Pek Lan Toh, Nursaida Mohamad Zaber, Veerendra Dakulagi and Zairi Ismael Rizman
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e-ISSN |
1819-6608 |
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On Pages
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491-496
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Volume No. |
20
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Issue No. |
8
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Issue Date |
June 28, 2025
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DOI |
https://doi.org/10.59018/042563
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Keywords |
drive current, feature size, FinFET, linear current, saturation current, sub-threshold current.
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Abstract
This paper presents a comprehensive framework that encompasses the design, characterization, and in-depth analysis of a 3-nm strained n-channel SiGe FinFET and its conventional Si counterpart. The integrity of our design is firmly established through intricate simulations that precisely replicate the transistor's output and transfer characteristics. It is particularly noteworthy that these characteristics harmoniously align with the well-established benchmarks defining an operational MOSFET. By comparing the performance of both transistors, we reveal the distinct advantages of the strained FinFET. By employing the silicon-on-insulator (SOI) substrate configuration, the leakage currents of both FinFETs are found to be comparatively low. It is also observed that the strained tri-gate transistor delivers a more robust drive current. This phenomenon is attributed to the enhanced carrier mobility induced by the compressive strain within the silicon channel. Additionally, we lay out in detail the design specifications underpinning the architecture of the transistor.
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