An efficient implementation of Hybrid Signcryption Processor using Flexible Encryption and Signature Techniques
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Full Text |
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Author |
Senthil Murugan M., Bhuvana B. P. and Jayabharathi P.
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e-ISSN |
1819-6608 |
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On Pages
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1730-1744
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Volume No. |
18
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Issue No. |
15
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Issue Date |
October 10, 2023
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DOI |
https://doi.org/10.59018/0823214
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Keywords |
hybrid signcryption, flexible encryption, hash function, ECC processor, Xilinx tool, FPGA.
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Abstract
In today’s digital era, with the enormous growth in the Internet of Things, everyday humans utilize IoT in various applications such as banking, online transactions, purchasing data forwarding, etc. Cryptography is all about the design and implementation of protocols that keep the data safe and secure from third parties. The design of the cryptographic processor present in the Field Programmable Gate Array (FPGA) incurs more power, area, and throughput. In this article, an Efficient Hybrid Signcryption Processor (EHSP) which operates based on the principle of encryption and signature is proposed. Generally, a hybrid signcryption operation comprises of Data Encapsulation Method (DEM) and Key Encapsulation Method (KEM). and in EHSP, we utilize the improved form of the Modified Kurosawa and Desmedt (MKD) hash scheme to encapsulate the key; the Elliptic Curve Cryptography (ECC) processor is used to encapsulate the message. The ECC processor is designed in a flexible manner and the flexibility is achieved by the flexible bit-serial multiplier, which reduces the power, and area consumption and maximizes the throughput. The proposed EHSP architecture is designed and simulated in Xilinx tool with various field programmable gate array families such as Virtex4 (XC4VLX60), Virtex5 (XC5VLX50), and Virtex7 (XC7V330T). The simulation result depicts the efficiency of the proposed EHSP design with respect to total power consumption, utilization of hardware, and throughput.
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