Optimized systolic array filters with noise classification for extracting FECG
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Author |
Preethi D., Sasikala G., Baranidharan V., Gnanaprakash V., Kumaran G. and Mohan Sai Kumar
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e-ISSN |
1819-6608 |
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On Pages
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2349-2363
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Volume No. |
18
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Issue No. |
21
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Issue Date |
January 10, 2024
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DOI |
https://doi.org/10.59018/1123287
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Keywords |
QRS Feature extraction using LDA, social spider optimization, systolic array filter, distance metric, glitch avoidance circuit using MUX.
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Abstract
To preserve the lives of both mother and foetus during the early phases of childbirth, heart abnormality diagnosis is essential. In remote places where understanding of maternal care is limited, the death rate caused by carelessness or a failure to detect abnormalities is still a problem. The signal will contain various external or internal noise sources to isolate the key components of the foetal heart rate from the mother's belly during labour. The likelihood that the genuine signal would be misinterpreted and result in a false report will increase in the presence of such noise sources. Although there are many software programs available for extracting the QRS features from foetal ECG signals, it is unavoidable that specialized hardware is required for a significant reduction in both area and power. This paper's main goal is to extract the QRS complex using LDA, then improve Social Spider classifier performance using the suggested TAODV as a distance metric calculator, and then compare against existing methods to discover sounds that are distorting the normal heart rate. Systolic array filter with suggested Glitch Avoidance Circuit employing MUX is simulated using Cadence Virtuoso in 65nm technology to remove noise from the observed QRS complex. Over 100 records with the necessary examples from MIT-BIH Arrhythmia were used in the simulations, and it was discovered that MATLAB 2010b was used to adopt a unique technique for classifying noise. The suggested TAODV-based SSA classifier's accuracy is 96.8%, whereas the accuracy of a filter with a glitch avoidance circuit is 96.13%. The primary benefit of these strategies comprises cutting-edge hardware and computational solutions.
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