Performance optimized group decomposition Dadda multiplier for DSP applications
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Author |
Suguna T., Kalaiyarasi D., C. Padma, R. Kiran Kumar, Padarti Vijaya Kumar and K. Venkata Lakshmi Keerthi
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e-ISSN |
1819-6608 |
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On Pages
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188-196
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Volume No. |
20
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Issue No. |
4
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Issue Date |
April 12, 2025
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DOI |
https://doi.org/10.59018/022531
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Keywords |
digital signal processing, full adder, wallace tree multiplier, dadda multiplier, grouping and decomposition multiplier, 5:2 logical adder.
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Abstract
This study introduces an extremely fast grouping and decomposition multiplier, providing a novel method of binary multiplication. The suggested multiplier combines the Wallace tree and Dadda multiplier with an innovative grouping and decomposition method such that a total number of partial products and critical path delay are minimized. The full adder used in the proposed multiplier structure is designed by using the GDI technique. The proposed multiplier is implemented using a 45 nm CMOS technology and evaluated against state-of-the-art binary multipliers in terms of speed, power consumption, and area. It is observed from the results that the suggested multiplier has improved performance when compared with existing multipliers. It is concluded that the PDP of the proposed 8-bit Group Decomposition Multiplier (PGDM) with the mentioned multipliers is reduced by 68.11%, 65.63% and 30.72% when compared with the 8-bit Wallace tree, Dadda multiplier and Group Decomposition (GD) multiplier respectively and hence concluded that the proposed multiplier design can be employed in DSP applications for high-speed digital signal processing applications including audio and video processing.
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