The design and verification of a SFIFO module using system verilog based UVM
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Full Text |
Pdf
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Author |
Sanjay Sidibhai Keshvala, Prativa Pranav Saraswala and Farah Moazzamkhan Pathan
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e-ISSN |
1819-6608 |
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On Pages
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2010-2018
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Volume No. |
20
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Issue No. |
23
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Issue Date |
February 10, 2026
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DOI |
https://doi.org/10.59018/1225223
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Keywords |
synchronous FIFO, UVM, System Verilog, RTL design, verification, code coverage, functional coverage.
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Abstract
The increasing complexity of Integrated Circuits (ICs) and System-on-Chip (SoC) designs necessitates robust and scalable verification methodologies to ensure functionality, reduce bugs, and shorten time-to-market. Traditional directed test benches are no longer sufficient to meet these verification demands. This paper presents the design of a Synchronous First- In-First-Out (SFIFO) buffer using Verilog HDL and its functional verification using System Verilog and Universal Verification Methodology (UVM). The FIFO is designed with a dual-port RAM structure, enabling concurrent read and write operations in a single clock domain. A comprehensive UVM testbench has been developed that includes sequencers, drivers, monitors, scoreboards, and a reference model. The simulation and verification were performed using Xilinx Vivado and QuestaSim.
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